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Silicon Labs /SiM3_NRND /SIM3L166_C /UART_0 /CLKDIV

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Interpret as CLKDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIV1)CLKDIV

CLKDIV=DIV1

Description

Clock Divider

Fields

CLKDIV

Clock Divider.

0 (DIV1): Divide by 1.

1 (DIV2): Divide by 2.

2 (DIV4): Divide by 4.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data